`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/03/16 18:39:46
// Design Name: 
// Module Name: hilo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module hilo(
    input logic clk,
    input logic res,

    //write port
    input logic [1:0] we,
    //input logic [31:0] hi_i,
    //input logic [31:0] lo_i,

    input logic [63:0] hilo_i,

    //read port
    output logic [31:0] hi_o,
    output logic [31:0] lo_o

    );

    always @(posedge clk) begin
        if(res) begin
            hi_o <= 32'b0;
            lo_o <= 32'b0;
        end else if((we == 2'b01)) begin
            //hi_o <= hi_i;
            hi_o <= hilo_i[63:32];
        end else if((we == 2'b10)) begin
            //lo_o <= lo_i;
            lo_o <= hilo_i[31: 0];
        end else if((we == 2'b11)) begin
            hi_o <= hilo_i[63:32];
            lo_o <= hilo_i[31: 0];
        end
    end
endmodule
